The present invention relates to a semiconductor device and particularly to a technique which is effectively applicable to a semiconductor device having a power transistor and a Schottky barrier diode (SBD) on one and the same semiconductor substrate.
As a semiconductor device used as a switching device in a power amplifier or a power supply circuit there is known, for example, a power transistor called power MISFET (Metal Insulator Semiconductor Field Effect Transistor). The power MISFET has a structure wherein plural transistor cells comprising fine patterns of MISFETs are connected in parallel to obtain a large power. Power MISFETs called vertical type and horizontal type are known. As to the vertical type, one called a trench gate structure is also known.
MISFET indicates an insulated gate type field effect transistor wherein a gate insulating film (insulating film) is interposed between a channel forming region (semiconductor) and a gate electrode. One wherein the gate insulating film is formed by a silicon oxide film is generally called MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Moreover, one wherein an electric current flows in the thickness (depth) direction of a semiconductor substrate is called a vertical type, while one wherein an electric current flows in the surface direction of a semiconductor substrate is called a horizontal type. Further, one having a channel (conductive passage) of electrons in a channel forming region between source and drain regions (i.e., under a gate electrode) is called n type (or n-channel conductor type), and one having a channel of holes is called p type (or p-channel conductive type). The trench gate structure indicates a gate structure wherein in the interior of a trench formed in one main surface of a semiconductor substrate there is formed a gate electrode through a gate insulating film. As to the power MISFET of the trench gate structure, it is described in Japanese Published Unexamined Patent Application No. Hei 7 (1995)-249770 for example.
FIG. 19 is a circuit diagram of a conventional synchronous rectification type DC/DC converter using power MISFETs and FIG. 20 is a timing chart of a power MISFET for main switch and a power MISFET for synchronous rectification both shown in FIG. 19. In FIG. 19, Q1 denotes a power MISFET for main switch, Q2 denotes a power MISFET for synchronous rectification, BD1 and BD2 denote body diodes, and SBD denotes a Schottky barrier diode. The body diodes BD1 and BD2 are incorporated in the power MISFETs respectively and are connected in parallel with the power MISFETs. The Schottky barrier diode SBD is connected in parallel with the power MISFET Q2 for synchronous rectification.
In the synchronous rectification type DC/DC converter shown in FIG. 19, a period called “Dead time” is set as shown in FIG. 20 so as to prevent a lead-through current caused by simultaneous turning ON of both Q1 and Q2. In this period there flow an electric current like B in FIG. 19. In this case, a circuit loss can be decreased by connecting a Schottky barrier diode smaller in forward voltage (VF) than the body diode BD2 in parallel with the power MISFET Q2 for synchronous rectification.
The use of the Schottky barrier diode is essential in such a circuit. In this connection, a semiconductor device is disclosed, for example, in Japanese Published Unexamined Patent Application No. Hei 10 (1998)-150140 wherein a semiconductor chip with a power MISFIT mounted thereon and a semiconductor chip with a Schottky barrier diode mounted thereon are sealed with a single seal member. Further, a semiconductor device with both a power MISFET of the trench gate structure and a Schottky barrier diode mounted on a single semiconductor substrate is disclosed, for example, in Japanese Published Unexamined Patent Application No. Hei 11 (1999)-154748.